Learn the Basics of FPGA Design

Explore our free and comprehensive tutorials covering the three major hardware description languages (HDL) which are used in the design and verification of FPGAs.


A hardware description language which is popular amongst engineers in europe.


The most popular hardware description language for FPGA engineers based in the USA

System Verilog

An extension of the verilog language which is primarily intended for FPGA verification

Who is John?

A headshot for John Darvill, the main author of fpgatutorial.com
John is the founder and main author of fpgatutorial.com. He has been designing FPGAs for more than 10 years whilst working at large tech companies and research institutes in the UK and Germany.

On this site, John teaches you the basics of the most commonly used languages for FPGA design – VHDL, Verilog and System Verilog (coming soon). 

You can also read more advanced, practical guidance on a wide range of FPGA related topics in his blog.

Latest Posts

June 9, 2021
Using the Always Block to Model Sequential Logic in SystemVerilog

In this post we discuss the coding methods we can use to model basic sequential logic circuits using the SystemVerilog always block

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May 27, 2021
Continuous Assignment and Combinational Logic in SystemVerilog

In this post we talk about continuous assignment before looking at some of techniques we can use to model combinational logic in systemverilog

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May 21, 2021
An introduction to SystemVerilog Operators

In this post we look at the different operators which we can use in our SystemVerilog designs.

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May 12, 2021
Creating Custom Types in SystemVerilog using Typedef, Enum and Struct

In this post we look at how we can create our own custom data types in SystemVerilog using enum, typedef and struct

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April 17, 2021
SystemVerilog Dynamic Arrays and Queues

In this post we talk about how we use dynamic arrays, queues and associative arrays in SystemVerilog

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April 6, 2021
An Introduction to SystemVerilog Arrays

In this post we talk about static arrays and how we can use them in our SystemVerilog designs

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