Learn the Basics of FPGA Design

Explore our free and comprehensive tutorials covering the three major hardware description languages (HDL) which are used in the design and verification of FPGAs.

VHDL

A hardware description language which is popular amongst engineers in europe.

Verilog

The most popular hardware description language for FPGA engineers based in the USA

System Verilog

An extension of the verilog language which is primarily intended for FPGA verification

Who is John?

A headshot for John Darvill, the main author of fpgatutorial.com
John is the founder and main author of fpgatutorial.com. He has been designing FPGAs for more than 10 years whilst working at large tech companies and research institutes in the UK and Germany.

On this site, John teaches you the basics of the most commonly used languages for FPGA design – VHDL, Verilog and System Verilog (coming soon). 

You can also read more advanced, practical guidance on a wide range of FPGA related topics in his blog.

Latest Posts

November 16, 2020
Writing Reusable Verilog Code using Generate and Parameters

In this post we look at how we use parameters and generate blocks to write reusable verilog modules.

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November 2, 2020
Using Tasks and Functions in Verilog

In this post we discuss subprograms and how we use them to write more efficient verilog code.

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October 12, 2020
An Introduction to Loops in Verilog

In this post we look at the different types of loop which we can use in our verilog designs.

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October 11, 2020
If Statements and Case Statements in Verilog

In this post we talk about two of the most commonly used sequential statements in verilog - the if statement and case statement

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September 30, 2020
How to Write a Basic Module in SystemVerilog

In the first post in this series we talk about how we structure SystemVerilog designs and how this relates to the hardware being described.

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August 16, 2020
How to Write a Basic Verilog Testbench

In this post we talk about testing our verilog based designs using basic test benches.

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