Learn the Basics of FPGA Design

Explore our free and comprehensive tutorials covering the three major hardware description languages (HDL) which are used in the design and verification of FPGAs.

VHDL

A hardware description language which is popular amongst engineers in europe.

Verilog

The most popular hardware description language for FPGA engineers based in the USA

System Verilog

An extension of the verilog language which is primarily intended for FPGA verification

Who is John?

A headshot for John Darvill, the main author of fpgatutorial.com
John is the founder and main author of fpgatutorial.com. He has been designing FPGAs for more than 10 years whilst working at large tech companies and research institutes in the UK and Germany.

On this site, John teaches you the basics of the most commonly used languages for FPGA design – VHDL, Verilog and System Verilog (coming soon). 

You can also read more advanced, practical guidance on a wide range of FPGA related topics in his blog.

Latest Posts

July 30, 2021
An Introduction to Tasks in SystemVerilog

In this post we look at tasks in SystemVerilog and how we use them to write code which can be reused.

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July 23, 2021
An Introduction to Functions in SystemVerilog

In this post we discuss functions and how we use them to write SystemVerilog code which is reusable.

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June 20, 2021
An Introduction to Loops in SystemVerilog

In this post we look at the different types of loop which we can use in SystemVerilog.

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June 17, 2021
If Statements and Case Statements in SystemVerilog

In this post we talk about two of the most commonly used constructs in SystemVerilog - the if statement and the case statement. We have seen in a previous post how use procedural blocks such as the always block to write SystemVerilog code which executes sequentially. We can also use a number of statements within […]

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June 9, 2021
Using the Always Block to Model Sequential Logic in SystemVerilog

In this post we discuss the coding methods we can use to model basic sequential logic circuits using the SystemVerilog always block

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May 27, 2021
Continuous Assignment and Combinational Logic in SystemVerilog

In this post we talk about continuous assignment before looking at some of techniques we can use to model combinational logic in systemverilog

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