On this page you will find a series of tutorials introducing FPGA design with verilog. These tutorials take you through all the steps required to start using verilog and are aimed at total beginners.

If you haven’t already done so, it is recommended that you read the posts which introduce the FPGA development process first. These give an overview of all the stages required to design an FPGA. This information will give you some important basic background knowledge which will help with these verilog tutorials.

A picture of the underside of a CPU
In the first post in this series we talk about how Verilog designs are structured and how this relates to the hardware being described.
A picture showing a pile of types faces as used in an old fashion printing press
In this post we talk about the different types we can use in verilog.
A black board with 1 + 1 = 2 written on it in white chalk
In this post we look at the different operators which we can use in our verilog designs.
A picture of a number of electronic chips mounted on a PCB.
In this post we talk about continuous assignment before looking at some of techniques we can use to model combinational logic in verilog
The top half of an analog pocket watch.
In this post we discuss the coding methods we can use to model basic sequential logic circuits using Verilog.
A picture of some electronic test equipment placed on top of a work bench
In this post we talk about testing our verilog based designs using basic test benches.
If Statements and Case Statements in Verilog
In this post we talk about two of the most commonly used sequential statements in verilog - the if statement and case statement
Looking up at the sky from the centre of a spiralling buidling
In this post we look at the different types of loop which we can use in our verilog designs.
A computer screen showing the source code for a function
In this post we discuss subprograms and how we use them to write more efficient verilog code.
A bag for recyclable rubbish surrounded by brown leaves.
In this post we look at how we use parameters and generate blocks to write reusable verilog modules.

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