In these introductory posts we discuss the FPGA development process from start to finish. This includes synthesis, place and route, timing and verification. However, we do not look at the coding of FPGAs in detail in these posts.
If you are new to FPGAs then it is recommended to read the first post before reading through the VHDL tutorials or Verilog tutorials which cover programming in more depth. This post is an overview of the entire process which will be useful for understanding the concepts we discuss in the programming tutorials.
The other posts in this section feature a more detailed discussion of each stage of the FPGA development process. These are useful resources for building a more in depth understanding of each of the stages in the design life cycle.