SystemVerilog

On this page you will find a series of tutorials introducing SystemVerilog for FPGA design and verification. These tutorials take you through all the steps required to start using SystemVerilog and are aimed at total beginners.

If you haven’t already done so, it is recommended that you read the posts which introduce the FPGA development process first. These give an overview of all the stages required to design an FPGA. This information will give you some important basic background knowledge which will help with these tutorials.

A picture of the underside of a CPU
In the first post in this series we talk about how we structure SystemVerilog designs and how this relates to the hardware being described.
A picture showing a pile of types faces as used in an old fashion printing press
In this post we talk about the different data types which we can use in SystemVerilog based designs and testbenches.
A metal plate with a grid of raised squares on it
In this post we talk about static arrays and how we can use them in our SystemVerilog designs
Different colored chalk stacked in a pile.
In this post we talk about how we use dynamic arrays, queues and associative arrays in SystemVerilog

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